7500=3-Stage Non-interlocking Code Fetch Pipeline|2-Stage Non-interlocking Data Fetch Pipeline
8000=64 and 128 Bit VLIW Molecules|Commit/Rollback Architecture|Code Morphing Software (CMS)
[Registers]
1500=32-bit Integer, 80-bit FP
1505=32-bit Integer, 80-bit FP, 64-bit MM
1507=32-bit Integer, 80-bit FP, 64-bit MM
1600=32-bit Integer, 80-bit FP, 40 Entry RAT
1604=32-bit Integer, 80-bit FP, 64-bit MM, 40 Entry RAT
1603=32-bit Integer, 80-bit FP, 64-bit MM, 40 Entry RAT
1605=32-bit Integer, 80-bit FP, 64-bit MM, 40 Entry RAT
1606=32-bit Integer, 80-bit FP, 64-bit MM, 40 Entry RAT
1607=32-bit Integer, 80-bit FP, 64-bit MM, 40 Entry RAT
1608=32-bit Integer, 80-bit FP, 64-bit MM, 40 Entry RAT
1609=32-bit Integer, 80-bit FP, 64-bit MM, 40 Entry RAT
1610=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1611=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1612=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1613=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1614=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1615=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1616=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1617=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1618=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1619=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1620=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE, 40 Entry RAT
1700=32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE and SSE2
5500=32 Bit Integer, 80 Bit FP, 22 Entry RAT
5600=32 Bit Integer, 80 Bit FP, 48 Entry RAT
3500=32 Bit Integer, 80 Bit FP, 40 Entry RAT
3505=32 Bit Integer, 80 Bit FP, 64 Bit MM, 48 Entry RAT
3506=32 Bit Integer, 80 Bit FP, 64 Bit MM, 48 Entry RAT
3507=32 Bit Integer, 80 Bit FP, 64 Bit MM, 69 Entry RAT
3508=32 Bit Integer, 80 Bit FP, 64 Bit MM, 69 Entry RAT
3509=32 Bit Integer, 80 Bit FP, 64 Bit MM, 69 Entry RAT
3600=32 Bit Integer, 80 Bit FP, 64 Bit MM|24 Entry 32-Bit 9x Read 8x Write IFFRF (Integer RAT)|88 Entry 90-Bit 5x Read 5x Write FPRF (FP RAT)
3700=32 Bit Integer, 80 Bit FP, 64 Bit MM|24 Entry 32-Bit 9x Read 8x Write IFFRF (Integer RAT)|88 Entry 90-Bit 5x Read 5x Write FPRF (FP RAT)
4500=32 Bit Integer, 80 Bit FP, 32 Entry RAT
4600=32 Bit Integer, 80 Bit FP, 64 Bit MM, 32 Entry RAT
4603=32 Bit Integer, 80 Bit FP, 64 Bit MM, Separate FP and MM
4604=32 Bit Integer, 80 Bit FP, 64 Bit MM, Separate FP and MM
4605=32 Bit Integer, 80 Bit FP, 64 Bit MM, Separate FP and MM
4606=32 Bit Integer, 80 Bit FP, 64 Bit MM, Separate FP and MM
6500=32 Bit Integer, 80 Bit FP, 64 Bit MM
7500=32 Bit Integer, 80 Bit FP, 64 Bit MM
8000=32 Bit Integer, 80 Bit FP, 64 Bit MM|64x/48x (Primary/Shadowed) 32 Bit General Purpose Registers|32x/16x (Primary/Shadowed) 80 Bit FP General Registers
[Pipeline Depth]
1500=2 (Shared) plus 2 x 3 (Dual Pipeline) Stages
1505=3 (Shared) plus 2 x 3 (Dual Pipeline) Stages
1507=3 (Shared) plus 2 x 3 (Dual Pipeline) Stages
1600=12 (In-order) plus 2 (Out-of-order) Stages
1700=20 Stages
5500=7 Stages
5600=6 Stages
3500=3 (In-order) plus 3 (Out-of-order) Stages
3505=6 Stages
3506=6 Stages
3507=6 Stages
3508=6 Stages
3509=6 Stages
3600=10 (Integer), 15 (FP)
3700=10 (Integer), 15 (FP)
4500=1 (Shared), 2x 4+2 In-/Out-of-order (Dual Pipeline) Stages,|4x FP plus 4x FP Store Queue
4600=1 (Shared), 2x 4+2 In-/Out-of-order (Dual Pipeline) Stages,|4x FP plus 6x FP Store Queue
4603=12 Stages (includes 7 RISC Stages for Execution),|6 additional Stages for FPU Instructions
4604=12 Stages (includes 7 RISC Stages for Execution),|6 additional Stages for FPU Instructions|8 Instruction Integer-to-FP FIFO Queue
4605=12 Stages (includes 7 RISC Stages for Execution),|6 additional Stages for FPU Instructions|8 Instruction Integer-to-FP FIFO Queue
4606=12 Stages (includes 7 RISC Stages for Execution),|6 additional Stages for FPU Instructions|8 Instruction Integer-to-FP FIFO Queue
6500=4 Stages
7500=8 Stages
8000=7 (Integer), 10 (FP)
[Instruction Decoder]
1500=2x IA-32/Cycle
1600=3x IA-32/Cycle, 6x ╡OPs/Cycle
1700=1x IA-32/Cycle
5500=1x IA-32/Cycle
5600=1-2x IA-32/Cycle, 1-4x ROPs/Cycle
3500=1-4x IA-32/Cycle, 4x ROPs/Cycle
3505=1-2x IA-32/Cycle, 4x ROPs/Cycle
3506=1-2x IA-32/Cycle, 4x ROPs/Cycle
3507=1-2x IA-32/Cycle, 4x ROPs/Cycle
3508=1-2x IA-32/Cycle, 4x ROPs/Cycle
3509=1-2x IA-32/Cycle, 4x ROPs/Cycle
3600=Direct and Vector Path, Up to 3x IA-32/Cycle|Up to 3x MOPs/Cycle, Up to 6x ROPs/Cycle
3700=Direct and Vector Path, Up to 3x IA-32/Cycle|Up to 3x MOPs/Cycle, Up to 6x ROPs/Cycle
4500=2x IA-32/Cycle
4600=2x IA-32/Cycle
4603=1x IA-32/Cycle, up to 3 ╡OPs/Cycle
4604=1x IA-32/Cycle, up to 3 ╡OPs/Cycle
4605=1x IA-32/Cycle, up to 3 ╡OPs/Cycle
4606=1x IA-32/Cycle, up to 3 ╡OPs/Cycle
6500=1x IA-32/Cycle
6502=1x IA-32/Cycle, up to 2x MMX or 3DNow!/Cycle, up to 4 ╡OPs/Cycle
6503=1x IA-32/Cycle, up to 2x MMX or 3DNow!/Cycle, up to 4 ╡OPs/Cycle
6504=1x IA-32/Cycle, up to 2x MMX or 3DNow!/Cycle, up to 4 ╡OPs/Cycle
6505=1x IA-32/Cycle, up to 2x MMX or 3DNow!/Cycle, up to 4 ╡OPs/Cycle
7500=Up to 3x IA-32/Cycle
8000=Code morphing Software (CMS)|Interprets and/or Translates x86 Code into VLIW Code
[Execution Units]
1500=2x Integer, Pipelined FPU
1505=2x Integer/MMX, Pipelined FPU
1507=2x Integer/MMX, Pipelined FPU
1600=2x ALU, Load, Store Address, Store Data, Pipelined FPU
1603=2x ALU/MMX, Load, Store Address, Store Data, Pipelined FPU
1605=2x ALU/MMX, Load, Store Address, Store Data, Pipelined FPU
1606=2x ALU/MMX, Load, Store Address, Store Data, Pipelined FPU
1607=2x ALU/MMX, Load, Store Address, Store Data, Pipelined FPU
1608=2x ALU/MMX, Load, Store Address, Store Data, Pipelined FPU
1609=2x ALU/MMX, Load, Store Address, Store Data, Pipelined FPU
1610=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1611=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1612=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1613=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1614=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1615=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1616=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1617=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1618=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1619=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU
1620=2x ALU/MMX/SSE, Load, Store Adress, Store Data, Pipelined FPU